/*
 * Fast Ethernet Controller (FEC) driver.
 * Copyright (c) 2006 Michael Broughton (mbobowik@telusplanet.net)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */


#ifndef FEC_H
#define	FEC_H


#include <asm/cacheflush.h>
#include <asm/coldfire.h>


#define TX_TIMEOUT		(2*HZ)


/*
 * Maximum frame length. Usually 1500 plus 18 or 22.
 */
#define MAX_FL			1518

/*
 * Receive buffer size. Must be a power of two in the range 256-2048.
 */
#define RX_BUF_SIZE		2048

/*
 * Padding at the end of each receive buffer. Fixes an overflow issue on some
 * ColdFire parts when running in 10baseT mode. Must have a value in {0,16,64}.
 * When the receive buffer size equals 2048, this must be set to 16 or 64.
 */
#define RX_BUF_PADDING		16

/*
 * Base two logarithm of the number of pages to allocate for the buffer
 * descriptor table.
 */
#define BD_TABLE_PAGE_ORDER	0

/*
 * Base two logarithm of the number of pages to allocate for receive buffers.
 */
#define RX_BUF_PAGE_ORDER	3

#define RX_BUF_LEN		(RX_BUF_SIZE-RX_BUF_PADDING)

#define BD_TABLE_LEN		((1<<BD_TABLE_PAGE_ORDER)*PAGE_SIZE)
#define RX_BUF_COUNT		((1<<RX_BUF_PAGE_ORDER)*PAGE_SIZE/RX_BUF_SIZE)

#define TX_BD_TABLE_LEN		(BD_TABLE_LEN/4)
#define TX_SB_TABLE_LEN		(BD_TABLE_LEN/8)
#define TX_AL_TABLE_LEN		(BD_TABLE_LEN/8)
#define RX_BD_TABLE_LEN		(RX_BUF_COUNT*sizeof(struct bd))
#define RX_BF_TABLE_LEN		(RX_BUF_COUNT*RX_BUF_SIZE)

#define TX_BD_COUNT		(TX_BD_TABLE_LEN/sizeof(struct bd))
#define TX_SB_COUNT		(TX_SB_TABLE_LEN/sizeof(struct sk_buff *))
#define TX_AL_COUNT		(TX_AL_TABLE_LEN/sizeof(unsigned long))
#define RX_BD_COUNT		(RX_BUF_COUNT)
#define RX_BF_COUNT		(RX_BUF_COUNT)


#define FEC_INTERRUPT_COUNT	13


#define TX_SKB_UNALIGNED(a)	((unsigned short)(((unsigned long)(a)) & 0x3))


#define HASH_BITS		6
#define CRC32_POLY		0xedb88320
#define CRC2HASH(crc)	(((crc) >> (32 - HASH_BITS)) & (~-(1<<HASH_BITS)))


/*
 * Macro's for dealing with buffer descriptor indices. The number of bd's must
 * be a power of two for these to work.
 */
#define RX_BD_IDX_INC(i)	(((i)+1)&(RX_BD_COUNT-1))
#define TX_BD_IDX_INC(i)	(((i)+1)&(TX_BD_COUNT-1))

#define TX_BD_IDX_DIST(h,t)	(((t)-(h))&(TX_BD_COUNT-1))


/*
 * FEC status/control registers
 */
struct fec_csr {
	unsigned long	reserved0;
	/* Interrupt Event Register */
	unsigned long	EIR;
	/* Interrupt Mask Register */
	unsigned long	EIMR;
	unsigned long	reserved1;
	/* Receive Descriptor Active Register */
	unsigned long	RDAR;
	/* Transmit Descriptor Active Register */
	unsigned long	TDAR;
	unsigned long	reserved2[3];
	/* Ethernet Control Register */
	unsigned long	ECR;
	unsigned long	reserved3[6];
	/* MII Data Register */
	unsigned long	MMFR;
	/* MII Speed Control Register */
	unsigned long	MSCR;
	unsigned long	reserved4[7];
	/* MIB Control/Status Register */
	unsigned long	MIBC;
	unsigned long	reserved5[7];
	/* Receive Control Register */
	unsigned long	RCR;
	unsigned long	reserved6[15];
	/* Transmit Control Register */
	unsigned long	TCR;
	unsigned long	reserved7[7];
	/* Physical Address Low Register */
	unsigned long	PALR;
	/* Physical Address High + Type Field */
	unsigned long	PAUR;
	/* Opcode + Pause Duration */
	unsigned long	OPD;
	unsigned long	reserved8[10];
	/* Upper 32 bits of Individual Hash Table */
	unsigned long	IAUR;
	/* Lower 32 bits of Individual Hash Table */
	unsigned long	IALR;
	/* Upper 32 bits of Group Hash Table */
	unsigned long	GAUR;
	/* Lower 32 bits of Group Hash Table */
	unsigned long	GALR;
	unsigned long	reserved9[7];
	/* Transmit FIFO  Watermark */
	unsigned long	TFWR;
	unsigned long	reserved10;
	/* FIFO Receive Bound Register */
	unsigned long	FRBR;
	/* FIFO Receive Start Register */
	unsigned long	FRSR;
	unsigned long	reserved11[11];
	/* Pointer to Receive Descriptor Ring */
	unsigned long	ERDSR;
	/* Pointer to Transmit Descriptor Ring */
	unsigned long	ETDSR;
	/* Maximum Receive Buffer Size */
	unsigned long	EMRBR;
};

#define FEC_EIR_HBERR		((unsigned long)0x80000000)
#define FEC_EIR_BABR		((unsigned long)0x40000000)
#define FEC_EIR_BABT		((unsigned long)0x20000000)
#define FEC_EIR_GRA		((unsigned long)0x10000000)
#define FEC_EIR_TXF		((unsigned long)0x08000000)
#define FEC_EIR_TXB		((unsigned long)0x04000000)
#define FEC_EIR_RXF		((unsigned long)0x02000000)
#define FEC_EIR_RXB		((unsigned long)0x01000000)
#define FEC_EIR_MII		((unsigned long)0x00800000)
#define FEC_EIR_EBERR		((unsigned long)0x00400000)
#define FEC_EIR_LC		((unsigned long)0x00200000)
#define FEC_EIR_RL		((unsigned long)0x00100000)
#define FEC_EIR_UN		((unsigned long)0x00080000)
#define FEC_EIR_CLEAR_ALL	((unsigned long)0xffffffff)
#define FEC_EIR_ERR		(FEC_EIR_HBERR | FEC_EIR_LC | FEC_EIR_RL | \
					FEC_EIR_UN)

#define FEC_EIMR_HBERR		((unsigned long)0x80000000)
#define FEC_EIMR_BABR		((unsigned long)0x40000000)
#define FEC_EIMR_BABT		((unsigned long)0x20000000)
#define FEC_EIMR_GRA		((unsigned long)0x10000000)
#define FEC_EIMR_TXF		((unsigned long)0x08000000)
#define FEC_EIMR_TXB		((unsigned long)0x04000000)
#define FEC_EIMR_RXF		((unsigned long)0x02000000)
#define FEC_EIMR_RXB		((unsigned long)0x01000000)
#define FEC_EIMR_MII		((unsigned long)0x00800000)
#define FEC_EIMR_EBERR		((unsigned long)0x00400000)
#define FEC_EIMR_LC		((unsigned long)0x00200000)
#define FEC_EIMR_RL		((unsigned long)0x00100000)
#define FEC_EIMR_UN		((unsigned long)0x00080000)
#define FEC_EIMR_MASK_ALL	((unsigned long)0x00000000)
#define FEC_EIMR_ERR		(FEC_EIMR_HBERR | FEC_EIMR_LC | FEC_EIMR_RL | \
								FEC_EIMR_UN)

#define FEC_RDAR_ACTIVE		((unsigned long)0x01000000)

#define FEC_TDAR_ACTIVE		((unsigned long)0x01000000)

#define FEC_ECR_ETHER_EN	((unsigned long)0x00000002)
#define FEC_ECR_RESET		((unsigned long)0x00000001)
#define FEC_ECR_OFF		((unsigned long)0x00000000)

#define FEC_MMFR_READ(id,reg) \
			((unsigned long)(0x60020000 | (((id) & 0x1f) << 23) | \
			(((reg) & 0x1f) << 18)))
#define FEC_MMFR_READ_MASK	((unsigned long)0x0000ffff)
#define FEC_MMFR_WRITE(id,reg,val) \
			((unsigned long)(0x50020000 | (((id) & 0x1f) << 23) | \
			(((reg) & 0x1f) << 18) | ((val) & 0xffff)))

#define FEC_MSCR_MII_SPEED	((unsigned long)((((MCF_CLK/500000)+5)/10)<<1))

#define FEC_RCR_MAX_FL(len)	((unsigned long)(((len) & 0x7ff) << 16))
#define FEC_RCR_FCE		((unsigned long)0x00000020)
#define FEC_RCR_BC_REJ		((unsigned long)0x00000010)
#define FEC_RCR_PROM		((unsigned long)0x00000008)
#define FEC_RCR_MII_MODE	((unsigned long)0x00000004)
#define FEC_RCR_DRT		((unsigned long)0x00000002)
#define FEC_RCR_LOOP		((unsigned long)0x00000001)

#define FEC_TCR_RFC_PAUSE	((unsigned long)0x00000010)
#define FEC_TCR_TFC_PAUSE	((unsigned long)0x00000008)
#define FEC_TCR_FDEN		((unsigned long)0x00000004)
#define FEC_TCR_HBC		((unsigned long)0x00000002)
#define FEC_TCR_GTS		((unsigned long)0x00000001)

#define FEC_EMRBR_R_BUF_SIZE(size)	((unsigned long)((size) & 0x7f0))


/*
 * Buffer Descriptor and status/control field definitions
 */
struct bd {
	unsigned short	sc;
	unsigned short	length;
	unsigned long	address;
};

/* Empty */
#define FEC_RX_BD_SC_E		((unsigned short)0x8000)
/* Receive Software Ownership 1 */
#define FEC_RX_BD_SC_RO1	((unsigned short)0x4000)
/* Wrap */
#define FEC_RX_BD_SC_W		((unsigned short)0x2000)
/* Receive Software Ownership 2 */
#define FEC_RX_BD_SC_RO2	((unsigned short)0x1000)
/* Last in Frame */
#define FEC_RX_BD_SC_L		((unsigned short)0x0800)
/* Miss */
#define FEC_RX_BD_SC_M		((unsigned short)0x0100)
/* Broadcast */
#define FEC_RX_BD_SC_BC		((unsigned short)0x0080)
/* Multicast */
#define FEC_RX_BD_SC_MC		((unsigned short)0x0040)
/* Frame Length Violation */
#define FEC_RX_BD_SC_LG		((unsigned short)0x0020)
/* Non-Octet Aligned Frame */
#define FEC_RX_BD_SC_NO		((unsigned short)0x0010)
/* CRC Error */
#define FEC_RX_BD_SC_CR		((unsigned short)0x0004)
/* Overrun */
#define FEC_RX_BD_SC_OV		((unsigned short)0x0002)
/* Truncated */
#define FEC_RX_BD_SC_TR		((unsigned short)0x0001)
#define FEC_RX_BD_SC_ERR	(FEC_RX_BD_SC_NO | FEC_RX_BD_SC_CR | \
					FEC_RX_BD_SC_OV | FEC_RX_BD_SC_TR)

/* Ready */
#define FEC_TX_BD_SC_R		((unsigned short)0x8000)
/* Transmit Software Ownership 1 */
#define FEC_TX_BD_SC_TO1	((unsigned short)0x4000)
/* Wrap */
#define FEC_TX_BD_SC_W		((unsigned short)0x2000)
/* Transmit Software Ownership 2 */
#define FEC_TX_BD_SC_TO2	((unsigned short)0x1000)
/* Last in Frame */
#define FEC_TX_BD_SC_L		((unsigned short)0x0800)
/* Transmit CRC */
#define FEC_TX_BD_SC_TC		((unsigned short)0x0400)
/* Transmit Bad CRC */
#define FEC_TX_BD_SC_ABC	((unsigned short)0x0200)


#define fec_flush_dcache()		__flush_dcache_all()
#define fec_flush_dcache_line(l)	__flush_cache_line(l)


#define FEC_RES(n,s,e,f) 	\
	{ .name = (n), .start = (s), .end = (e), .flags = (f) }

#define FEC_RES_MEM(n,s,e) FEC_RES((n),(s),(e),IORESOURCE_MEM)
#define FEC_RES_IRQ(i,n) FEC_RES((n),(i),(i),IORESOURCE_IRQ)


int fec_platform_init(void);
void fec_platform_cleanup(void);


#endif /* FEC_H */